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Renesas Electronics /R7FA6M3AH /GLCDC /BG_MON

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Interpret as BG_MON

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)EN 0 (0)VEN 0 (0)SWRST

EN=0, SWRST=0, VEN=0

Description

Background Plane Setting Status Monitor Register

Fields

EN

Background plane generation module operation state monitor.

0 (0): Operation is stopped.

1 (1): Operation is in progress.
VEN

Entire module internal operation reflection control signal monitor.The signal state for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal.

0 (0): The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is negated.

1 (1): The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is asserted.
SWRST

Entire module SW reset state monitor.

0 (0): The entire module is in the SW reset state.

1 (1): The entire module is released from the SW reset state.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data